Post by williamplayer on Jan 20, 2014 13:08:41 GMT
IBM Research Report
Graphene Field-Effect Transistors with Self-Aligned Gates
We present a new device fabrication process that produces graphene-based field-effect transistors with self-aligned gates. This process utilizes the inherent nucleation inhibition of atomic-layer-deposited films with the graphene surface to achieve electrical isolation of the gate electrode from the source/drain electrodes while maintaining electrical access to the graphene channel. Self-alignment produces access lengths of 15 - 20 nm, which allows for improved device stability, performance, and a minimal normalized contact resistance of 540Ωμm.
Due to its unique electronic properties, graphene is a material of intense investigation for both scientific and technological applications. Specifically, the high mobility of charge carriers in graphene combined with the ability to modulate the carrier concentration by an external electric field has made graphene-based field-effect transistors (FETs) promising candidates for future high frequency applications. Recently, graphene FETs have been demonstated to operate at cut-off frequencies (fT) as high as 100 GHz. Additional increases in fT will be achieved through further improvement of both the constituent device ma terials and the device design. One of the critical factors limiting the ultimate performance of graphene FETs is the parasitic series resistance between the source/drain contacts and the gated graphene channel. While these access regions serve to reduce the parasitic capacitance between the gate and the source/drain electrodes, their resistance results in a lower current that hinders the device performance. It is therefore desirable to minimize the access resistance (RA) as much as possible. This is especially crucial in the downscaling of graphene devices because RA can become comparable to the gated channel resistance (RG) and adversely affect the device behavior. In conventional silicon-based FETs, the access resistance is reduced by doping these ungated regions through ion implantation. The two-dimensional structure of graphene negates the use of this technique, which would inevitably damage the fragile carbon lattice.
Read Full Report: domino.research.ibm.com/library/cyberdig.nsf/papers/5B67ADC8FEDC71A3852577270050C066/$File/rc24987.pdf
Graphene Field-Effect Transistors with Self-Aligned Gates
We present a new device fabrication process that produces graphene-based field-effect transistors with self-aligned gates. This process utilizes the inherent nucleation inhibition of atomic-layer-deposited films with the graphene surface to achieve electrical isolation of the gate electrode from the source/drain electrodes while maintaining electrical access to the graphene channel. Self-alignment produces access lengths of 15 - 20 nm, which allows for improved device stability, performance, and a minimal normalized contact resistance of 540Ωμm.
Due to its unique electronic properties, graphene is a material of intense investigation for both scientific and technological applications. Specifically, the high mobility of charge carriers in graphene combined with the ability to modulate the carrier concentration by an external electric field has made graphene-based field-effect transistors (FETs) promising candidates for future high frequency applications. Recently, graphene FETs have been demonstated to operate at cut-off frequencies (fT) as high as 100 GHz. Additional increases in fT will be achieved through further improvement of both the constituent device ma terials and the device design. One of the critical factors limiting the ultimate performance of graphene FETs is the parasitic series resistance between the source/drain contacts and the gated graphene channel. While these access regions serve to reduce the parasitic capacitance between the gate and the source/drain electrodes, their resistance results in a lower current that hinders the device performance. It is therefore desirable to minimize the access resistance (RA) as much as possible. This is especially crucial in the downscaling of graphene devices because RA can become comparable to the gated channel resistance (RG) and adversely affect the device behavior. In conventional silicon-based FETs, the access resistance is reduced by doping these ungated regions through ion implantation. The two-dimensional structure of graphene negates the use of this technique, which would inevitably damage the fragile carbon lattice.
Read Full Report: domino.research.ibm.com/library/cyberdig.nsf/papers/5B67ADC8FEDC71A3852577270050C066/$File/rc24987.pdf